1. Field of the Invention
The present invention relates to processing signals, and more particularly to a system and method for performing duty-cycle correction of clock and other frequency signals.
2. Background of the Related Art
Synchronous chips often use a latch design in which a logic path propagates in one phase (high or low) of a clock signal. In chips of this type, phase paths are influenced by duty-cycle distortion of the clock signal. This mainly occurs because of process variations and/or changes in the level of the voltage supply (e.g., changes in transistor characteristics with voltage supply level). As a result, if one of the clock phases in a synchronous chip is reduced, data may be sampled earlier than expected and this may lead to phase-path failure.
To overcome this problem, the frequency of the clock signal can be reduced to a value that compensates for and thus restores the original phase duration. For example, a 2% duty-cycle distortion in a 2 GHz clock frequency results in a 10 ps reduction of the clock phase. Thus, to restore the original clock phase period of 250 ps, the clock frequency may be reduced to 1920 MHz.
In higher frequency CPUs, phase-path designs have increasingly been used. As presently implemented, this design has a number of drawbacks, not the least of which include increasing the sensitivity of the maximum operating frequency of the CPU relative to duty-cycle distortion of a core clock signal. In fact, core clock duty-cycle distortion is one of the main factors that limits the maximum frequency of the CPU.
Conventional high-performance CPUs use static duty-cycle correction circuits. These circuits are based on a digitally controlled phase shifter that varies the clock phase duration with a predetermined resolution. The clock phase is shifted in automatic test equipment based on test programs to optimize the maximum frequency of the CPU. This approach is undesirable for at least two reasons. First, valuable tester time is wasted which makes the procedure inefficient. Second, testing is performed at only one voltage point, which tends to diminish the effectiveness of the overall process.